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MB15U36
Description
Dual PLL Frequency Synthesizer with On-Chip Prescaler
Packages
The Fujitsu MB15U36 dual PLL is a serial input frequency synthesizer with 2.0 GHz and 1.2 GHz prescalers.The prescalers both have a selectable dual modulus division ratio of 64/65 or 128/129 enabling pulse swallow operation. The MB15U36 utilizes a refined charge pump design (Fujitsu's Super Charger)that provides fast tuning along with low spurious noise and phase noise characteristics. The MB15U36 is ideally suited for digital mobile communications, including GSM, DCS1800, PCS1900, IS-136, IS-95 and ISM-band applications.
20-pin plastic SSOP , FPT-20P-M03
Features
* Very low spurious and phase noise characteristics * Wide operating voltage: 3.0 to 5.5 volts * Low operating current: 6.0 mA @ VCC = 3 volts (typical) * Power-saving current: 10A (typical) * Wide operating temperature: -40 to +85C * Plastic 20-pin SSOP package * Reference counter: - 15-bit programmable divider: 3 to 32767 * 18-bit programmable divider: - Binary 7-bit swallow counter: 0 to 127 - Binary 11-bit programmable counter: 3 to 2047 * Software selectable charge pump current: - Do output 1.0 or 4.0 mA @ VCC = 3V * Evaluation Kits available
Parameter RF frequency of operation, max. IF/RF frequency of operation, max Low power supply voltage Low power supply current Prescaler divide ratios Power-saving function
MB15U36 2.0 GHz 1.2 GHz 3 - 5.5V 6.0 mA @ 3V RF1, RF2 = 64/65 or 128/129 10A typical
MB15U36
Table of Contents
Pin Descriptions: MB15U36 ................................................................................................................................................... 4 Block Diagram: MB15U36 ..................................................................................................................................................... 5 Absolute Maximum Ratings .................................................................................................................................................... 6 Recommended Operating Conditions........................................................................................................................................ 6 Handling Precautions...................................................................................................................................................... 6 Electrical Characteristics........................................................................................................................................................ 7 Measurement Circuit (fin, OSCIN Input Sensitivity) .................................................................................................................... 9 Typical Electrical Characteristics ........................................................................................................................................... 10 Reference Information ................................................................................................................................................... 13 Functional Descriptions ....................................................................................................................................................... 14 Serial Data Input .......................................................................................................................................................... 14 Table 1: Control Bits ..................................................................................................................................................... 14 Shift Register Configuration for the Programmable Reference Counter .......................................................................... 14 Shift Register Configuration for the Programmable Counter ........................................................................................ 15 Table 2: Binary 14-bit Programmable Reference Counter Data Setting................................................................................. 15 Table 3: Phase Comparator Phase Switching Data Setting.................................................................................................. 15 Table 4: Charge Pump Current Setting ............................................................................................................................ 16 Table 5: Charge Pump Output Impedance Setting ............................................................................................................. 16 Table 6: LD/fOUT Output Select Data Setting.................................................................................................................... 16 Table 7: Binary 11-bit Programmable Counter Data Setting............................................................................................... 16 Table 8: Binary 7-bit Swallow Counter Data Setting ......................................................................................................... 17 Table 9: Prescaler Data Setting ...................................................................................................................................... 17 Power Saving Mode (Intermittent Mode Control Circuit) ........................................................................................................ 17 Table 10: Power Save Internal Shutdown Logic.................................................................................................................. 17 Serial Data Input Timing ..................................................................................................................................................... 18 Table 11: Timing Parameters.......................................................................................................................................... 18 Power-ON Timing Diagram ........................................................................................................................................... 18 Phase Detector Output Waveform .......................................................................................................................................... 19 Application Example ........................................................................................................................................................... 20 Application Example: Fastlock Mode ..................................................................................................................................... 21 Ordering Information .......................................................................................................................................................... 22 Package Dimensions ........................................................................................................................................................... 23
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Dual PLL Frequency Synthesizer with On-Chip Prescaler
Pin Descriptions: MB15U36
Pin No. SSOP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Pin Name Vcc1 Vp1 Do1 GND1 fin1 Xfin1 GND1 OSCIN OSCOUT LD/fOUT Clock Data LE GND2 Xfin2 fin2 GND2 Do2 Vp2 Vcc2 I/O - I O - I I - I O O I I I - I I - O I - Descriptions Power supply voltage input pin for the RF1-PLL section, the shift register, and the oscillator input buffer. When poweris OFF, latched data for RF1-PLL is lost. Power supply for the RF1-PLL charge pump. (Independent of pin 19) Charge pump output for the RF1-PLL section. Phase detector characteristics can be reversed using the FC-bit. Ground for the RF1-PLL section. Prescaler input for the RF1-PLL. Connection to an external VCO should be via AC coupling. Prescaler complimentary input for the RF1-PLL section. This pin should be grounded via a small capacitor. Ground for the RF1-PLL section. External TCXO reference oscillator input or connection to crystal. TCXO should be connected via AC coupling. Oscillator output or connection to crystal. Lock detect signal output (LD) or phase comparator monitoring output (fout). The output signal is selected by the LDS and FDS bits in the serial programming data. Clock input for the 22-bit shift register. One bit of data is shifted into the shift register on a rising edge of the clock. Serial data input. Data is transferred to the corresponding latch (RF1-ref counter, RF1-prog. counter, RF2-ref. counter, RF2-prog. counter) according to the control bits settings in the serial programming data. Load enable signal input. When the LE bit is set to "H", data in the shift register is transferred to the corresponding latch ac cording to the control bits settings in the serial programming data. Ground for the RF2-PLL section. Prescaler complimentary input for the RF2-PLL section. This pin should be grounded via a small capacitor. Prescaler input for the RF2-PLL. Connection to an external VCO should be via AC coupling. Ground for the RF2-PLL section. Charge pump output for the RF2-PLL section. Phase detector characteristics can be reversed using the FC-bit. Power supply for the RF2-PLL charge pump. (Independent of pin 2) Power supply voltage input pin for the RF2-PLL section. When power is OFF, latched data for RF2-PLL is lost.
Vcc1 Vp1 Do1 GND1 fin1 Xfin1 GND1 OSCIN OSCOUT LD/fOUT
1 2 3 4 5 6 7 8 9 10
20 19 18 17 TOP 16 VIEW 15 14 13 12 11
Vcc2 Vp2 Do2 GND2 fin2 Xfin2 GND2 LE Data Clock
(FPT-20P-M03)
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Fujitsu Microelectronics, Inc.
MB15U36
Block Diagram: MB15U36
VCC2 20 GND2 14 17 Vp2 19
2-bit latch
SW PS
7-bit latch
Binary 7-bit swallow counter (RF2-PLL)
11-bit latch
Binary 11-bit programmable counter (RF2-PLL)
fpRF2
Phase comp.
(RF2-PLL)
Charge pump
(RF2-PLL)
18 Do2
fin2 16 Xfin2 15
Prescaler
(RF2-PLL) 64/65, 128/129
Lock Detect
(RF2-PLL)
5-bit latch
FC CMC ZC LDS FDS
15-bit latch
Binary 15-bit programmable ref. counter (RF2-PLL)
LDRF2
OSCOUT 9 frRF2 OSCIN 8
Selector
LDRF2
FC
CMC
ZC
LDS FDS
OR 5-bit latch fin1 5 Xfin1 6 Prescaler
(RF1-PLL) 64/65, 128/129
Binary 15-bit programmable ref. counter (RF1-PLL)
LDRF1
frRF1
frRF2 frRF1 fpRF2
10 LD/fout
15-bit latch LDRF1 Lock Detect
(RF1-PLL)
fpRF1
SW
PS
Binary 7-bit swallow counter (RF1-PLL)
Binary 11-bit programmable counter (RF1-PLL)
Phase comp. fpRF1
(RF1-PLL)
Charge pump
(RF1-PLL)
3 Do1
2-bit latch
7-bit latch
11-bit latch
LE 13
Latch selector
Data 12 Clock 11
CC NN 12
22-bit shift register
1 Vcc1
47 GND2
2 Vp1
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Dual PLL Frequency Synthesizer with On-Chip Prescaler
Absolute Maximum Ratings
Parameter Power supply voltage Input voltage Output voltage Storage temperature Symbol Vcc1,2 Vp1,2 VI VO TSTG Rating -0.5 to +6.5 -0.5 to +6.5 -0.5 to +6.5 -0.5 to +6.5 -55 to +125 Unit V V V V C Note
WARNING: Semiconductor devices can be permanently damaged by the application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
Recommended Operating Conditions
Value Parameter Symbol Vcc Vp VI Ta Min. 3.0 3.0 GND -40 Typ. 5.0 5.0 - - Max. 5.5 5.5 VCC +85 Unit V V V C Note Vcc1 = Vcc2 Vcc1 = Vcc2 *1
Power supply voltage Input voltage Operating temperature
*1: Prescaler divide ratio is only 64/65 (SW = "L") at RF1. WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their Fujitsu representative beforehand.
Handling Precautions
* This device should be transported and stored in anti-static containers * This is a static-sensitive device; take proper anti-ESD precautions. Ensure that personnel and equipment are properly grounded. Cover workbenches with grounded conductive mats. * Always turn the power supply off before inserting or removing the device from its socket. * Protect leads with a conductive sheet when handling or transporting PC boards with devices.
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MB15U36
Electrical Characteristics
(VCC =3.0 to 5.5V,Ta = -40 to +85C)
Value Parameter Symbol fin1 = 2000 MHz fosc = 12 MHz fin2 = 1200 MHz fosc = 12 MHz Vcc1 current at PS bitRF1, RF2 ="H" Vcc1 current at PS bit RF2 ="H" RF1-PLL RF2-PLL 500mVp-p minimm 50 load system (Refer to measurement circuit.) 50 load system (Refer to measurement circuit.) Condition Vcc = 5V Vcc = 3V Vcc = 5V Vcc = 3V Min. - - - - - - 100 50 3 -10 -10 0.5 VCC x 0.8 - VIH = Vcc VIL = Vcc VIH = Vcc VIL = Vcc IOH = -1 mA IOL = 1 mA IOH = -0.5 mA IOL = 0 .5 mA VCC = Vp = 5.0V 0.5V VDO Vp - 0.5V VCC = 5.0V VCC = 5.0V VCC = Vp = 5.0V VCC = Vp = 3.0V VCC = Vp = 5.0V VCC = Vp = 3.0V VCC = Vp = 5.0V VCC = Vp = 3.0V IDOL VCC = Vp = 5.0V VCC = 3.0V CMC bit = "L" CMC bit = "L" CMC bit = "L" CMC bit = "L" CMC bit = "H" CMC bit = "H" CMC bit = "H" CMC bit = "H" -1.0 -1.0 0 -100 Vcc -0.4 - Vcc -0.4 - - -1.0 - - - - - - - - - Typ. 6.0 3.5 3.0 2.5 0.1*3 0.1*3 - - - - - - - - - - - - - - - - - - - -1.25 -1.0 1.25 1.0 -5.0 -4.0 5.0 4.0 Max. - - - - 10 10 2000 1200 40 +2 +2 VCC - VCC x 0.2 +1.0 +1.0 +100 0 - V 0.4 - V 0.4 3.0 - 1.0 - - - - - - - - nA mA mA mA mA mA mA mA mA mA mA Unit mA mA mA mA A A MHz MHz MHz dBm dBm Vp-p V
Icc1*1 Power supply current Icc2*2 Ips1 Ips2 fin1*4 fin2*4 fOSC fin RF1-PLL Input sensitivity finRF2-PLL OSCIN Input voltage Data, Clock, LE Data, Clock, LE Input current OSCIN PfinRF2-PLL VOSC VIH VIL IIH*5 IIL*5 IIH IIL*5 VOH PfinRF1- PLL
Power saving current Operating frequency
A
A
LD/fOUT Output voltage Do1, Do2 High impedance cutoff current Do1, Do2 LD/fOUT
VOL
VDOH VDOL IOFF IOH*5 IOL IDOH*5
Output current Do1, Do2
IDOL IDOH*5
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Dual PLL Frequency Synthesizer with On-Chip Prescaler
Value Parameter IDOL/IDOH Charge pump current characteristics IDO vs VDO IDO vs Ta Symbol IDOMT*6 IDOVD*7 IDOTA*8 VDO = VCC/2 0.5V VDO VCC - 0.5V -40xC Ta +85C, VDO = Vp/2 Condition Min. - - - Typ. 3 15 10 Max. - - - Unit % % %
*1: *2: *3: *4: *5: *6: *7: *8:
Conditions: Vcc1 = 5.0V, Ta = +25C, in locking state. Conditions: Vcc2 = 5.0V, Ta = +25C, in locking state. Conditions: Vcc = 5.0V, fOSC = 12.8MHz (-2dBm),Ta = +25C AC coupling, 1000pF capacitor is connected under the condition of min. operating frequency. The symbol "-" (minus) means direction of current flow. VCC = 5.0 V, Ta = +25C (|I3| - |I4|)/[(|I3| + |I4|)/2] X 100(%) VCC = 5.0 V, Ta = +25C [(|I2| - |I1|)/2]/[(|I1| + |I2|)/2] X 100(%) (Applied to each IDOL, IDOH) VCC = 5.0 V, [|IDO(85C) - IDO(-40C)|/2]/[|IDO(85C) + IDO(-40C)|/2] X 100(%) (Applied to each IDOL, IDOH)
I1 IDOL
I3 I2
IDOH
I2
I4 I1 0.5 Vcc/2 Vcc - 0.5 V Vcc
Charge Pump Output Voltage (V)
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Fujitsu Microelectronics, Inc.
MB15U36
Measurement Circuit (For Measuring Input Sensitivity of fin and OSCin)
fOUT
Oscilloscope
Sig. Gen.
1000 pF 50
1000 pF Sig. Gen. 1000 pF 50 .1 F .1 F
LD/fOUT 10
OSCOUT 9
OSCIN 8
GND1 7
Xfin1 6
fin1 5
GND1 4
Do1 3
Vp1 2
Vcc1 1
MB15U36
11 12 13 14 15 16 17 18 19 20
From Controller
Clock
Data
LE
GND2
Xfin2
fin2
GND2
Do2
Vp2
Vcc2
1000 pF .1 F Sig. Gen. 1000 pF 50 .1 F
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Dual PLL Frequency Synthesizer with On-Chip Prescaler
Typical Electrical Characteristics: MB15U36
Input Sensivity of fin (RF1) versus Input Frequency
VfinRF1 VS. finRF1
PfinRF1 vs. finRF1
10 0
Pfin R F1 (dBm VfinRF1 [dBm] )
SPEC
-10 -20 -30 -40 -50 0 500 1000 1500 finRF1 (MHz) finRF1 [MHz] 2000 2500 3000
P fin(dB m )@ Vfin[dBm ]@ 5.5V Vfin[dBm ]@ 5.0V Pfin(dBm)@5.0V Vfin[dBm ]@ 4.5V Pfin(dBm)@4.5V Vfin[dBm ]@ 3.0V Pfin(dBm)@3.0V
Input Sensivity of fin (RF2) versus Input Frequency
VfinRF2 VS. finRF2
PfinRF2 vs. finRF2
10 0 VfinRF2 [dBm] Pfin R F 2 (dBm ) -10 -20 -30 -40 -50 0 500 1000 1500 2000
SPEC
P fin(dB m )@ 5.5V Vfin[dBm]@5.5V
Pfin(dBm)@5.0V Vfin[dBm]@5.0V Pfin(dBm)@4.5V Vfin[dBm]@4.5V Pfin(dBm)@3.0V Vfin[dBm]@3.0V
finRF2 [MHz] finRF2 (MHz)
Input Sensivity of OSCIN versus Input Frequency
Vfosc VS. fosc
PfinOSC vs. finRF2
10 0
SPEC
Pfin O S C [dBm] ) VOSC (dBm
-10 -20 -30 -40 -50 0 50 100 fosc [MHz] 150 200 250 VOSCin[dBm]@5.5V P O S C (dB m )@ 5.5V PO SC (dBm)@5.0V VOSCin[dBm]@5.0V VOSCin[dBm]@4.5V PO SC (dBm)@4.5V VOSCin[dBm]@3.0V PO SC (dBm)@3.0V
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MB15U36
Typical Electrical Characteristics: MB15U36
Conditions: Ta = +25C Do output current: 1 x Do mode
IDOH VS. VDOH
IDOH - VDOH
DOH "H" level output voltage VDOH (V
8 7 6 5 4 3 2 1 0 0 -0.5 -1 -1.5 -2 "H" level output voltage IDOH (mA) "H" level output current IDOH (mA) -2.5 -3 Vcc=5V Vcc=3V
"H" level output voltage V
(V)
I VS. VDOL IDOLDOL - VDOL
8.0 "L" "L" level output voltage VDOL VDOL (V level output voltage (V) 7.0 6.0 5.0 Vcc=5V 4.0 3.0 2.0 1.0 0.0 0 0.5 1 1.5 2 2.5 --Id "L" level output voltage oIDOL (mA)IDOL(mA) "L" level output current " -- 3 Vcc=3V
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Dual PLL Frequency Synthesizer with On-Chip Prescaler
Typical Electrical Characteristics: MB15U36
Conditions: Ta = +25C Do output current: 4 x Do mode
IDOH - VDOH IDOH VS. VDOH
"H" level "H" level output voltage VDOH (V) output voltage VDOH (V
8 7 6 5 4 3 2 1 0 0 -1 -2 -3 -4 -5 "H" voltage current DOH (mA) "H" level outputlevel output IDOHI(mA) -6 -7 -8 Vcc=5V Vcc=3V
IDOLIDOL -VDOL VS. VDOL 8.0
"L" level output voltage (V) "L" level outputvoltage VDOLVDOL (V
7.0 6.0 5.0 4.0 3.0 2.0 1.0 0.0 0 1 2 3 4 5 "L" level outputlevel output current I (mA) "L" voltage IDOL (mA)
DOL
Vcc=5V Vcc=3V
6
7
8
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Fujitsu Microelectronics, Inc.
MB15U36
Reference Information: MB15U36
Test Circuit SG OSC fin
IN
Do
LPF
fVCO = 1780 MHz K V = 58 MHz/V fr = 200 KHz fOSC = 10 MHz LPF
V C C = VP = 3.0V V V C O = 5.0V Ta = +25 C CP: 1mA mode 3.3K
Spectrum Analyzer
750pF VCO
6 8 0 0 6 8 0 0 pF
150pF
Typical plots measure with the test circuit are shown below. Each plot shows lock up time, phase noise, and reference leakage.
RF PLL Reference Leakage @ 200 kHz offset = -80.3 dBc
RF PLL Phase Noise @ max within loop band = -66.5 dBc/Hz
-80.3 dBc
RF PLL Lock Up Time = 442s (1760.000 MHz 1800.000 MHz, within 1kHz)
RF PLL Lock Up Time = 387s (1800.000 MHz 1760.000 MHz, within 1kHz)
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Dual PLL Frequency Synthesizer with On-Chip Prescaler
Functional Descriptions
The VCO output frequency can be calculated using the following equation: fVCO = {(M x N) + A} x fOSC / R (A < N) fVCO: M: N: A: fOSC: R: Output frequency of external voltage controlled oscillator (VCO) Preset divide ratio of dual modulus prescaler (64 or 128 for RF1-PLL or RF2-PLL2) Preset divide ratio of binary 11-bit programmable counter (3 to 2,047) Preset divide ratio of binary 7-bit swallow counter (0 A 127) Reference oscillation frequency Preset divide ratio of binary 14-bit programmable reference counter (3 to 32,767)
Serial Data Input
Serial data is entered using the Data, Clock, and LE pins. The serial data controls the programmable reference counters and the programmable counters separately. Binary serial data is entered through the Data pin when the LE pin is held low. One bit of data is shifted into the shift register on the rising edge of the Clock. When the LE signal pin is taken high, entered data is latched into the appropriate counters according to the control bit settings as follows:
Table 1. Control Bits
Control Bits CN1 L L H H CN2 L H L H Destination of Serial Data The programmable reference counter for the RF2-PLL The programmable reference counter for the RF1-PLL The programmable counter and the swallow counter for the RF2-PLL The programmable counter and the swallow counter for the RF1-PLL
Shift Register Configuration
Programmable Reference Counter
LSB Data Flow MSB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19 C M C
20 Z C
21 L D S
22 F D S
C N 1
C N 2
R 1
R 2
R 3
R 4
R 5
R 6
R 7
R 8
R 9
R 10
R 11
R 12
R 13
R 14
R 15
F C
CNT1, 2 R1 to R15 FC CMC ZC LDS/FDS
Control bits Divide ratio setting bits for the programmable reference counter (3 to 32,767) Phase control bit for the phase detector Charge pump current select bit Forced high impedance control for the charge pump LD/fOUT signal select bits
[Table 1] [Table 2] [Table 3] [Table 4] [Table 5] [Table 6]
Note: Input Data with MSB first.
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MB15U36
Functional Descriptions
Programmable Counter
LSB Data Flow MSB
1 C N 1
2 C N 2
3 A 1
4 A 2
5 A 3
6 A 4
7 A 5
8 A 6
9 A 7
10 N 1
11 N 2
12 N 3
13 N 4
14 N 5
15 N 6
16 N 7
17 N 8
18 N 9
19 N 10
20 N 11
21 S W
22 P
S
CNT1, 2 N1 to N11 A1 to A7 SW PS
Control bits Divide ratio setting bits for the programmable counter (3 to 2,047) Divide ratio setting bits for the swallow counter (0 to 127) Divide ratio setting bit for the prescalers (64/65 or 128/129 for the RF1-PLL and RF2-PLL) Power saving mode control bit
[Table 1] [Table 7] [Table 8] [Table 9] [Table 10]
Note: Input Data with MSB first.
Table 2. Binary 15-bit Programmable Reference Counter Data Setting
Divide Ratio (R) 3 4 . 32767 R 15 0 0 . 1 R 14 0 0 . 1 R 13 0 0 . 1 R 12 0 0 . 1 R 11 0 0 . 1 R 10 0 0 . 1 R 9 0 0 . 1 R 8 0 0 . 1 R 7 0 0 . 1 R 6 0 0 . 1 R 5 0 0 . 1 R 4 0 0 . 1 R 3 0 1 . 1 R 2 1 0 . 1 R 1 1 0 . 1
Note: Divide ratio less than 3 is prohibited.
Table 3. Phase Comparator Phase Switching Data Setting
DoRF1-PLL,RF2-PLL FCRF1-PLL,RF2-PLL = "H" fr > fp fr = fp fr < fp VCO polarity H Z L (1) FCRF1-PLL,RF2-PLL = "L" L Z H (2) VCO output frequency (1)
Notes: 1) Z = High-impedance 2) The FC bit should be set depending upon the VCO and LPF polarity VCO input voltage
(2)
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Dual PLL Frequency Synthesizer with On-Chip Prescaler
Functional Descriptions
Table 4. Charge Pump Current Setting (CMC)
CMC L H Current Value 1 x Do 4 x Do
Table 5. Charge Pump Output Impedance Setting (ZC)
ZC L H Do Output Impedance Normal output High impedance
Table 6. LD/fout Output Select Data Setting
LDSRF1 L L H H X X X X L L H H Note: X = Don't care LDSRF2 L H L H L L H H L H L H FDSRF1 L L L L L H L H H H H H FDSRF2 L L L L H L H L H H H H LD/fOUT Output Signal Disabled LD signal (RF2 lock detect) LD signal (RF1 lock detect) LD signal (RF1/RF2 lock detect) fOUT (Output frRF2) fOUT (Output frRF1) fOUT (Output fpRF2) fOUT (Output fpRF2) Fastlock RF2 counter reset RF1 counter reset RF1/RF2 counter reset
Table 7. Binary 11-bit Programmable Counter Data Setting
Divide Ratio (N) 3 4 . 2047 N 11 0 0 . 1 N 10 0 0 . 1 N 9 0 0 . 1 N 8 0 0 . 1 N 7 0 0 . 1 N 6 0 0 . 1 N 5 0 0 . 1 N 4 0 0 . 1 N 3 0 1 . 1 N 2 1 0 . 1 N 1 1 0 . 1
Note: Divide ratio less than 3 is prohibited.
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MB15U36
Functional Descriptions
Table 8. Binary 7-bit Swallow Counter Data Setting
Divide Ratio (A) 0 1 . 127 A 7 0 0 . 1 A 6 0 0 . 1 A 5 0 0 . 1 A 4 0 0 . 1 A 3 0 0 . 1 A 2 0 0 . 1 A 1 0 1 . 1
Note: Divide ratio (A) range = 0 to 127
Table 9. Prescaler Data Setting (SW)
Prescaler Divide Ratio RF1-PLL RF2-PLL SW = "L" 64/65 64/65 SW = "H" 128/129 128/129
Power-Saving Mode (Intermittent Mode Control)
* The intermittent mode control circuit greatly reduces the PLL power consumption by shuting down various internal functions, as shown in Table 10, depending upon the settings of the power save (PS) bits. Setting the PS bits to "H" enters the corresponding PLL into the power-saving mode. See the Electrical Characteristics chart for the specific value of current when in the power-saving mode. * The phase detector output, Do, becomes high impedance. * Serial data can be entered while in the power-saving mode. * Setting the PS pins "L" releases the power-saving mode, returning the selected PLL to normal operation. Note: When power (VCC) is first applied, the device must be in standby mode, PS = High, for at least 1s.
Table 10. Power Save Internal Shutdown Logic (PS)
PSRF2 H L H L PSRF1 H H L L RF2-PLL Counters OFF ON OFF ON RF1-PLL Counters OFF OFF ON ON OSC Input Buffer OFF ON ON ON
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Dual PLL Frequency Synthesizer with On-Chip Prescaler
Serial Data Input Timing
1st data Control bit Invalid data 2nd data
Data
MSB
LSB
Clock
t1 t7 t2 t3 t6
LE
t4 t5
Table 11. Timing Parameters
Parameter t1 t2 t3 t4 Min. 20 20 30 30 Typ. - - - - Max. - - - - Unit ns ns ns ns Parameter t5 t6 t7 Min. 100 20 100 Typ. - - - Max. - - - Unit ns ns ns
Notes: 1) On the rising edge of the clock, one bit of the data is transferred into the shift register. 2) LE should be set to "L" when the data is transferred into the shift register.
Power-ON Timing
OFF VCC Clock Data LE PS tPS 100 nS tV 1 S ON
(1)
(1) PS = H (power-saving mode) at Power-ON (2) Input serial data 1s later after power supply remains stable (VCC > 2.2V). (3) Release power-saving mode (PS: H AE L) 100ns later after setting serial data. 18
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(2)
(3)
MB15U36
Phase Detector Output Waveform
frRF1-PLL, RF2-PLL
fpRF1-PLL, RF2-PLL
tWU LD
tWL
(FC bit = "H") H DoRF1-PLL, RF2-PLL Z L
(FC bit = "L") DoRF1-PLL, RF2-PLL Z
Notes:
1) Phase error detection range: -2 to +2 2) Pulses on Do signal during locked state are output to prevent dead zone.
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Dual PLL Frequency Synthesizer with On-Chip Prescaler
Application Example
OUTPUT VCO LPF
3V
3V
TCXO 1000 pF 1000 pF Lock Detect 1000 pF .1 F .1 F
LD/fOUT 10
OSCOUT 9
OSCIN 8
GND1 7
Xfin1 6
fin1 5
GND1 4
Do1 3
Vp1 2
Vcc1 1
MB15U36
11 Clock From Controller 12 Data 13 LE 14 GND2 15 Xfin2 16 fin2 17 GND2 18 Do2 19 Vp2 20 Vcc2
1000 pF
1000 pF
3V
3V
.1 F
.1 F
OUTPUT VCO LPF
Notes: 1) Package Type: 20-pin SSOP 2) Clock, Data, LE: Insert a pull-down or pull-up resistor as needed to prevent oscillation when the terminals are left open.
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Application Example: Fastlock Mode
OUTPUT VCO LPF
3V
3V
TCXO 1000 pF 1000 pF 1000 pF .1 F .1 F
LD/fOUT 10
OSCOUT 9
OSCIN 8
GND1 7
Xfin1 6
fin1 5
GND1 4
Do1 3
Vp1 2
Vcc1 1
MB15U36
11 Clock From Controller 12 Data 13 LE 14 GND2 15 Xfin2 16 fin2 17 GND2 18 Do2 19 Vp2 20 Vcc2
1000 pF
1000 pF
3V
3V
.1 F OUTPUT VCO LPF
.1 F
Notes: 1) Package Type: 20-pin SSOP 2) Clock, Data, LE: Insert a pull-down or pull-up resistor as needed to prevent oscillation when the terminals are left open 3) The Fastlock mode is controlled by the LDS/FDS bits and the CMC RF1 bit. When the CMCRF1 bit is set to "H" (the RF1 charge pump current is increased 4x normal mode), the LD/fout pin (open drain output) is "L", enabling the parallel resistor in the loop filter. This effectively increases the LPF bandwidth, allowing the loop to lock faster. After the loop has locked onto a new frequency, the CMCRF1 bit is set to "L", forcing the LD/fout output pin into a high impedance state and returning the LPF bandwidth back to its original value.
Fujitsu Microelectronics, Inc.
21
Dual PLL Frequency Synthesizer with On-Chip Prescaler
Usage Precautions
To protect against damage by electrostatic discharge, note the following handling precautions: * * * * Store and transport devices in conductive containers. Use properly grounded workstations, tools, and equipment. Turn off power before inserting or removing this device into or from a socket. Protect leads with conductive sheet when transporting a board mounted device.
Ordering Information
Part Number Package
MB15U36PFV
20-pin, Plastic SSOP (FPT-20P-M03)
22
Fujitsu Microelectronics, Inc.
MB15U36
Package Dimensions
20-pin, Plastic SSOP (FPT-20P-M03)
* 6.500.10(.256.004)
* T hese dim e nsions do not include resin protrusion
1.25 .049
+0.20 -0.10 +.008 -.004
(Mounting height) 0.10(.004)
INDEX
* 4.400.10
(.173.004)
6.400.20 (.252.008)
5.40(.213) NOM
0.650.12 (.0256.0047)
0.22 .009
+0.10 -0.05 +.004 -.002
"A" 0.15 .006
+0.05 -0.02 +.002 -.001
Details of "A" part 0.100.10(.004.004) (STAND OFF)
5.85(.230)REF
0
10
0.500.20 (.020.008)
D im ensions in m m (inches)
Fujitsu Microelectronics, Inc.
23
1999 Fujitsu Microelectronics, Inc. All rights reserved. All company and product names are trademarks or registered trademarks of their respective owners. With respect to any information contained in this document, Fujitsu makes no warranties, express, implied or otherwise, including but not limited to warranty of merchantability or of fitness for a particular purpose, or warranty that such information shall be free from errors or that such errors shall be corrected, or warranty that such information shall be free from infringement or patents, patent applications, copyrights, semiconductor chip protection rights, trade secrets and other proprietary or legal rights of a third party. In no event will Fujitsu be responsible for any incidental or consequential damages arising out of use of this information. The information in this document does not convey any license under the copyrights, patent rights, or trademarks claimed and owned by Fujitsu Limited, its subsidiaries, or Fujitsu Microelectronics, Inc.
FUJITSU MICROELECTRONICS, INC.
Corporate Headquarters 3545 North First Street, San Jose, California 95134-1804 Tel: (800) 866-8608 Fax: (408) 922-9179 E-mail: fmicrc@fmi.fujitsu.com Web Site: http://www.fujitsumicro.com
Fujitsu Microelectronics, Inc. reserves the right to change products or specifications without notice. No part of this publication may be copied or reproduced in any form, or by any means, or transferred to any third party without prior written consent of Fujitsu Microelectronics, Inc. Printed in U.S.A. TC-DS-20806-5/99

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